// Copyright (C) 1953-2022 NUDT
// Verilog module name - tsnswitch 
// Version:V4.0.0.20221115
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//               
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module tsnswitch
#(
    parameter NUM_GMAC = 4,  
    parameter NUM_XGMAC = 0,	
    parameter INDEX_HCP = 4,
    parameter PTP_RX_OFFSET_XGMII = 16'd51,//51.2ns
    parameter PTP_TX_OFFSET_XGMII = 16'd58, 
    parameter PTP_RX_OFFSET_GMII = 16'd192,
    parameter PTP_TX_OFFSET_GMII = 16'd72,    
    parameter CLK125MHz_PERIOD = {8'd8,41'h0},//8ns
    parameter CLK156p25MHz_PERIOD = {8'd6,41'h0cccccccccc}//6.4ns
)
(
        i_clk
       
       ,i_hard_rst_n
       ,i_button_rst_n
       ,i_et_resetc_rst_n 

       ,i_gmii_rxclk      
       ,iv_gmii_rxd  
       ,i_gmii_rx_dv 
       ,i_gmii_rx_er 
       ,o_gmii_txclk        
       ,ov_gmii_txd  
       ,o_gmii_tx_en 
       ,o_gmii_tx_er 

       ,reset_clk_pulse
       ,ov_hardware_stage
	   ,o_s_pulse        
	   ,o_PTO0	   
	   ,o_PTO1	   
	   ,o_PTO2	   
	   ,o_PTO3
	   ,ov_frequency_cor
	   ,ov_schedule_period
	   ,ov_localclk	  	   
       ,o_cyclestart          

);

input                   i_clk;                  //125Mhz

input                   i_hard_rst_n;
input                   i_button_rst_n;
input                   i_et_resetc_rst_n;

//input       [39:0]		iv_local_counter;

output                  reset_clk_pulse;
output                  o_PTO0;	   
output                  o_PTO1;	   
output                  o_PTO2;	   
output                  o_PTO3;
output                  o_cyclestart; 
//input       
input      [NUM_GMAC-1:0]         i_gmii_rxclk    ;
input      [8*NUM_GMAC-1:0]       iv_gmii_rxd   ;
input      [NUM_GMAC-1:0]         i_gmii_rx_dv  ;
input      [NUM_GMAC-1:0]         i_gmii_rx_er  ;

output     [NUM_GMAC-1:0]         o_gmii_txclk;  
output     [8*NUM_GMAC-1:0]       ov_gmii_txd;
output     [NUM_GMAC-1:0]         o_gmii_tx_en;
output     [NUM_GMAC-1:0]         o_gmii_tx_er;

output     [2:0]                  ov_hardware_stage;
output     [48:0]                 ov_frequency_cor;
output     [10:0]                 ov_schedule_period;
output     [79:0]                 ov_localclk;
output                            o_s_pulse        ;

wire        [11:0]      wv_hcp_mid_hcp2tse                    ;
wire        [31:0]      wv_tse_ver_tse2hcp                    ;
wire                    w_rc_rxenable_hcp2tss                 ;
wire                    w_st_rxenable_hcp2tss                 ;
wire                    w_tsmp_lookup_table_key_wr_tse2hcp    ;
wire        [47:0]      wv_tsmp_lookup_table_key_tse2hcp      ;
wire        [32:0]      wv_tsmp_lookup_table_outport_hcp2tse  ;
wire                    w_tsmp_lookup_table_outport_wr_hcp2tse;

wire        [63:0]      wv_command_hcp2hub        ;   
wire                    w_command_wr_hcp2hub      ; 
wire        [63:0]      wv_command_ack_hub2hcp    ;
wire                    w_command_ack_wr_hub2hcp  ; 

wire                    w_data_wr_hcp2tse   ;
wire        [8:0]       wv_data_hcp2tse     ;

wire        [8:0]       wv_data_tse2hcp     ;
wire                    w_data_wr_tse2hcp   ;     

//wire        [79:0]      wv_localclk_stc2swc;
wire                    w_local_cnt_rst_hcp2osm;
//wire                    w_tsn_or_tte_hcp2osm;
wire                    w_sync_step_mode_hcp2osm;
wire                    w_cyclestart;

wire        [39:0]      wv_local_counter_hcp2tss;

wire        [NUM_GMAC + NUM_XGMAC -1:0]       w_osm_req_tx_pulse_osm2hcp   ;
wire        [NUM_GMAC + NUM_XGMAC -1:0]       w_osm_resp_rx_pulse_osm2hcp  ;
wire        [NUM_GMAC + NUM_XGMAC -1:0]       w_osm_req_rx_pulse_osm2hcp   ;
wire        [NUM_GMAC + NUM_XGMAC -1:0]       w_osm_resp_tx_pulse_osm2hcp  ;

wire        w_sync_generate_pulse_hcp2tss;

assign  o_s_pulse=w_osm_resp_rx_pulse_osm2hcp[0];
assign  o_cyclestart=w_cyclestart;
//reset sync
wire                    w_core_rst_n;
wire        [NUM_GMAC-1:0]      wb_mac_rst_n;
                        
wire                    w_rst_n;

assign w_rst_n = i_hard_rst_n & i_button_rst_n & i_et_resetc_rst_n;

assign ov_hardware_stage = {1'b0,w_st_rxenable_hcp2tss,w_rc_rxenable_hcp2tss};

hardware_control_point 
#(
 .PTP_RX_OFFSET_XGMII(PTP_RX_OFFSET_XGMII)
,.PTP_TX_OFFSET_XGMII(PTP_TX_OFFSET_XGMII)
,.PTP_RX_OFFSET_GMII(PTP_RX_OFFSET_GMII)
,.PTP_TX_OFFSET_GMII(PTP_TX_OFFSET_GMII)
,.clk_period(CLK125MHz_PERIOD)
)
hardware_control_point_inst
(
 .i_clk                            (i_clk                     )
,.i_rst_n                          (w_core_rst_n              )  

,.i_tsnnic_or_tsnswitch            (1'b0                      )//1:tsnnic.  0:tsnswitch
,.ov_localclk                      (ov_localclk               )
//,.ov_frequency_cor				   (ov_frequency_cor          )
//,.o_local_cnt_rst                  (w_local_cnt_rst_hcp2osm   )     
//,.o_tsn_or_tte                     (w_tsn_or_tte_hcp2osm      )
,.o_sync_step_mode                 (w_sync_step_mode_hcp2osm  )

,.ov_local_counter                 (wv_local_counter_hcp2tss  )

,.i_data_wr_from_tss               (w_data_wr_tse2hcp      )
,.iv_data_from_tss                 (wv_data_tse2hcp           )  
,.ov_data_to_tss                   (wv_data_hcp2tse           )
,.o_data_wr_to_tss                 (w_data_wr_hcp2tse         )

,.i_gmii_rx_clk                      (i_clk)
,.i_gmii_rx_dv                       (1'b0 )
,.iv_gmii_rxd                        (9'b0 )
,.i_gmii_rx_er                       (1'b0 )
,.o_gmii_tx_clk                      ()
,.o_gmii_tx_en                       ()
,.ov_gmii_txd                        ()
,.o_gmii_tx_er                       ()

,.ov_local_id                      (wv_hcp_mid_hcp2tse                    ) 
,.iv_tss_ver                       (wv_tse_ver_tse2hcp                    ) 
,.o_rc_rxenable                    (w_rc_rxenable_hcp2tss                 ) 
,.o_st_rxenable                    (w_st_rxenable_hcp2tss                 )
 
,.i_tsmp_lookup_table_key_wr       (w_tsmp_lookup_table_key_wr_tse2hcp    )
,.iv_tsmp_lookup_table_key         (wv_tsmp_lookup_table_key_tse2hcp      )
,.ov_tsmp_lookup_table_outport     (wv_tsmp_lookup_table_outport_hcp2tse  )
,.o_tsmp_lookup_table_outport_wr   (w_tsmp_lookup_table_outport_wr_hcp2tse)

,.o_cyclestart                    ( w_cyclestart                        )
,.o_sync_ok                        (                             )

,.ov_command_tss               (wv_command_hcp2hub                    )
,.o_command_wr_tss             (w_command_wr_hcp2hub                  )        
,.iv_command_ack_tss           (wv_command_ack_hub2hcp                )
,.i_command_ack_wr_tss         (w_command_ack_wr_hub2hcp              )

, .i_osm_req_tx_pulse_p0           ( w_osm_req_tx_pulse_osm2hcp [0 ])     
,.i_osm_resp_rx_pulse_p0           (w_osm_resp_rx_pulse_osm2hcp [0 ])     
, .i_osm_req_rx_pulse_p0           ( w_osm_req_rx_pulse_osm2hcp [0 ])
,.i_osm_resp_tx_pulse_p0           (w_osm_resp_tx_pulse_osm2hcp [0 ])
                                                                  
, .i_osm_req_tx_pulse_p1           ( w_osm_req_tx_pulse_osm2hcp [1 ])     
,.i_osm_resp_rx_pulse_p1           (w_osm_resp_rx_pulse_osm2hcp [1 ])     
, .i_osm_req_rx_pulse_p1           ( w_osm_req_rx_pulse_osm2hcp [1 ])
,.i_osm_resp_tx_pulse_p1           (w_osm_resp_tx_pulse_osm2hcp [1 ])
                                                                 
, .i_osm_req_tx_pulse_p2           ( w_osm_req_tx_pulse_osm2hcp [2 ])     
,.i_osm_resp_rx_pulse_p2           (w_osm_resp_rx_pulse_osm2hcp [2 ])     
, .i_osm_req_rx_pulse_p2           ( w_osm_req_rx_pulse_osm2hcp [2 ])
,.i_osm_resp_tx_pulse_p2           (w_osm_resp_tx_pulse_osm2hcp [2 ])
                                                                  
, .i_osm_req_tx_pulse_p3           ( w_osm_req_tx_pulse_osm2hcp [3 ])     
,.i_osm_resp_rx_pulse_p3           (w_osm_resp_rx_pulse_osm2hcp [3 ])     
, .i_osm_req_rx_pulse_p3           ( w_osm_req_rx_pulse_osm2hcp [3 ])
,.i_osm_resp_tx_pulse_p3           (w_osm_resp_tx_pulse_osm2hcp [3 ])
                                                                  
, .i_osm_req_tx_pulse_p4           (1'b0)//( w_osm_req_tx_pulse_osm2hcp [4 ])     
,.i_osm_resp_rx_pulse_p4           (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [4 ])     
, .i_osm_req_rx_pulse_p4           (1'b0)//( w_osm_req_rx_pulse_osm2hcp [4 ])
,.i_osm_resp_tx_pulse_p4           (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [4 ])
                             
, .i_osm_req_tx_pulse_p5           (1'b0)//( w_osm_req_tx_pulse_osm2hcp [5 ])     
,.i_osm_resp_rx_pulse_p5           (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [5 ])     
, .i_osm_req_rx_pulse_p5           (1'b0)//( w_osm_req_rx_pulse_osm2hcp [5 ])
,.i_osm_resp_tx_pulse_p5           (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [5 ])
                                
, .i_osm_req_tx_pulse_p6           (1'b0)//( w_osm_req_tx_pulse_osm2hcp [6 ])     
,.i_osm_resp_rx_pulse_p6           (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [6 ])     
, .i_osm_req_rx_pulse_p6           (1'b0)//( w_osm_req_rx_pulse_osm2hcp [6 ])
,.i_osm_resp_tx_pulse_p6           (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [6 ])
                              
, .i_osm_req_tx_pulse_p7           (1'b0)//( w_osm_req_tx_pulse_osm2hcp [7 ])     
,.i_osm_resp_rx_pulse_p7           (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [7 ])     
, .i_osm_req_rx_pulse_p7           (1'b0)//( w_osm_req_rx_pulse_osm2hcp [7 ])
,.i_osm_resp_tx_pulse_p7           (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [7 ])
                                                                  
, .i_osm_req_tx_pulse_p8           (1'b0)//( w_osm_req_tx_pulse_osm2hcp [8 ])     
,.i_osm_resp_rx_pulse_p8           (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [8 ])     
, .i_osm_req_rx_pulse_p8           (1'b0)//( w_osm_req_rx_pulse_osm2hcp [8 ])
,.i_osm_resp_tx_pulse_p8           (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [8 ])
                                                                  
, .i_osm_req_tx_pulse_p9           (1'b0)//( w_osm_req_tx_pulse_osm2hcp [9 ])     
,.i_osm_resp_rx_pulse_p9           (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [9 ])     
, .i_osm_req_rx_pulse_p9           (1'b0)//( w_osm_req_rx_pulse_osm2hcp [9 ])
,.i_osm_resp_tx_pulse_p9           (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [9 ])
                                                                  
, .i_osm_req_tx_pulse_p10          (1'b0)//( w_osm_req_tx_pulse_osm2hcp [10])     
,.i_osm_resp_rx_pulse_p10          (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [10])     
, .i_osm_req_rx_pulse_p10          (1'b0)//( w_osm_req_rx_pulse_osm2hcp [10])
,.i_osm_resp_tx_pulse_p10          (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [10])
                                                                  
, .i_osm_req_tx_pulse_p11          (1'b0)//( w_osm_req_tx_pulse_osm2hcp [11])     
,.i_osm_resp_rx_pulse_p11          (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [11])     
, .i_osm_req_rx_pulse_p11          (1'b0)//( w_osm_req_rx_pulse_osm2hcp [11])
,.i_osm_resp_tx_pulse_p11          (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [11])
                                                                  
, .i_osm_req_tx_pulse_p12          (1'b0)//( w_osm_req_tx_pulse_osm2hcp [12])     
,.i_osm_resp_rx_pulse_p12          (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [12])     
, .i_osm_req_rx_pulse_p12          (1'b0)//( w_osm_req_rx_pulse_osm2hcp [12])
,.i_osm_resp_tx_pulse_p12          (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [12])
                                                                  
, .i_osm_req_tx_pulse_p13          (1'b0)//( w_osm_req_tx_pulse_osm2hcp [13])     
,.i_osm_resp_rx_pulse_p13          (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [13])     
, .i_osm_req_rx_pulse_p13          (1'b0)//( w_osm_req_rx_pulse_osm2hcp [13])
,.i_osm_resp_tx_pulse_p13          (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [13])
                                                                  
, .i_osm_req_tx_pulse_p14          (1'b0)//( w_osm_req_tx_pulse_osm2hcp [14])     
,.i_osm_resp_rx_pulse_p14          (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [14])     
, .i_osm_req_rx_pulse_p14          (1'b0)//( w_osm_req_rx_pulse_osm2hcp [14])
,.i_osm_resp_tx_pulse_p14          (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [14])
                                                                  
, .i_osm_req_tx_pulse_p15          (1'b0)//( w_osm_req_tx_pulse_osm2hcp [15])     
,.i_osm_resp_rx_pulse_p15          (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [15])     
, .i_osm_req_rx_pulse_p15          (1'b0)//( w_osm_req_rx_pulse_osm2hcp [15])
,.i_osm_resp_tx_pulse_p15          (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [15])
                                                                  
, .i_osm_req_tx_pulse_p16          (1'b0)//( w_osm_req_tx_pulse_osm2hcp [16])     
,.i_osm_resp_rx_pulse_p16          (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [16])     
, .i_osm_req_rx_pulse_p16          (1'b0)//( w_osm_req_rx_pulse_osm2hcp [16])
,.i_osm_resp_tx_pulse_p16          (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [16])
                                                                  
, .i_osm_req_tx_pulse_p17          (1'b0)//( w_osm_req_tx_pulse_osm2hcp [17])     
,.i_osm_resp_rx_pulse_p17          (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [17])     
, .i_osm_req_rx_pulse_p17          (1'b0)//( w_osm_req_rx_pulse_osm2hcp [17])
,.i_osm_resp_tx_pulse_p17          (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [17])
                                                                 
, .i_osm_req_tx_pulse_p18          (1'b0)//( w_osm_req_tx_pulse_osm2hcp [18])     
,.i_osm_resp_rx_pulse_p18          (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [18])     
, .i_osm_req_rx_pulse_p18          (1'b0)//( w_osm_req_rx_pulse_osm2hcp [18])
,.i_osm_resp_tx_pulse_p18          (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [18])
                                                                 
, .i_osm_req_tx_pulse_p19          (1'b0)//( w_osm_req_tx_pulse_osm2hcp [19])     
,.i_osm_resp_rx_pulse_p19          (1'b0)//(w_osm_resp_rx_pulse_osm2hcp [19])     
, .i_osm_req_rx_pulse_p19          (1'b0)//( w_osm_req_rx_pulse_osm2hcp [19])
,.i_osm_resp_tx_pulse_p19          (1'b0)//(w_osm_resp_tx_pulse_osm2hcp [19])
                                                                  
, .i_osm_req_tx_pulse_p20          (1'b0)     
,.i_osm_resp_rx_pulse_p20          (1'b0)     
, .i_osm_req_rx_pulse_p20          (1'b0)
,.i_osm_resp_tx_pulse_p20          (1'b0)

, .i_osm_req_tx_pulse_p21          (1'b0)
,.i_osm_resp_rx_pulse_p21          (1'b0)
, .i_osm_req_rx_pulse_p21          (1'b0)
,.i_osm_resp_tx_pulse_p21          (1'b0)
, .i_osm_req_tx_pulse_p22          (1'b0)
,.i_osm_resp_rx_pulse_p22          (1'b0)
, .i_osm_req_rx_pulse_p22          (1'b0)
,.i_osm_resp_tx_pulse_p22          (1'b0)
, .i_osm_req_tx_pulse_p23          (1'b0)
,.i_osm_resp_rx_pulse_p23          (1'b0)
, .i_osm_req_rx_pulse_p23          (1'b0)
,.i_osm_resp_tx_pulse_p23          (1'b0)
, .i_osm_req_tx_pulse_p24          (1'b0)
,.i_osm_resp_rx_pulse_p24          (1'b0)
, .i_osm_req_rx_pulse_p24          (1'b0)
,.i_osm_resp_tx_pulse_p24          (1'b0)
, .i_osm_req_tx_pulse_p25          (1'b0)
,.i_osm_resp_rx_pulse_p25          (1'b0)
, .i_osm_req_rx_pulse_p25          (1'b0)
,.i_osm_resp_tx_pulse_p25          (1'b0)
, .i_osm_req_tx_pulse_p26          (1'b0)
,.i_osm_resp_rx_pulse_p26          (1'b0)
, .i_osm_req_rx_pulse_p26          (1'b0)
,.i_osm_resp_tx_pulse_p26          (1'b0)
, .i_osm_req_tx_pulse_p27          (1'b0)
,.i_osm_resp_rx_pulse_p27          (1'b0)
, .i_osm_req_rx_pulse_p27          (1'b0)
,.i_osm_resp_tx_pulse_p27          (1'b0)
, .i_osm_req_tx_pulse_p28          (1'b0)
,.i_osm_resp_rx_pulse_p28          (1'b0)
, .i_osm_req_rx_pulse_p28          (1'b0)
,.i_osm_resp_tx_pulse_p28          (1'b0)
, .i_osm_req_tx_pulse_p29          (1'b0)
,.i_osm_resp_rx_pulse_p29          (1'b0)
, .i_osm_req_rx_pulse_p29          (1'b0)
,.i_osm_resp_tx_pulse_p29          (1'b0)
, .i_osm_req_tx_pulse_p30          (1'b0)
,.i_osm_resp_rx_pulse_p30          (1'b0)
, .i_osm_req_rx_pulse_p30          (1'b0)
,.i_osm_resp_tx_pulse_p30          (1'b0)
, .i_osm_req_tx_pulse_p31          (1'b0)
,.i_osm_resp_rx_pulse_p31          (1'b0)
, .i_osm_req_rx_pulse_p31          (1'b0)
,.i_osm_resp_tx_pulse_p31          (1'b0)

,.o_sync_generate_pulse            (w_sync_generate_pulse_hcp2tss)

);  


reset_top 
#(
    .NUM_GMAC(NUM_GMAC)
   ,.NUM_XGMAC(NUM_XGMAC)
)
reset_top_inst(
 .i_clk                (i_clk)
,.i_rst_n              (w_rst_n)
                    
,.ib_mac_rxclk         ({ i_gmii_rxclk} )
                    
,.o_core_rst_n         (w_core_rst_n)
,.ob_mac_rst_n          (wb_mac_rst_n)
);

reset_clock_check reset_clock_check_inst(
 .i_clk            (i_clk          )
,.i_rst_n          (w_core_rst_n   )

,.o_reset_clk_pulse(reset_clk_pulse)  
);

time_sensitive_switch 
#(
 .NUM_GMAC(NUM_GMAC) 
,.NUM_XGMAC(NUM_XGMAC) 
,.INDEX_HCP(INDEX_HCP)
,.PTP_RX_OFFSET_XGMII(PTP_RX_OFFSET_XGMII)
,.PTP_TX_OFFSET_XGMII(PTP_TX_OFFSET_XGMII)
,.PTP_RX_OFFSET_GMII(PTP_RX_OFFSET_GMII)
,.PTP_TX_OFFSET_GMII(PTP_TX_OFFSET_GMII)
,.CLK125MHz_PERIOD(CLK125MHz_PERIOD)
,.CLK156p25MHz_PERIOD(CLK156p25MHz_PERIOD)
)
time_sensitive_switch_inst(
 .i_clk                          (i_clk                     )
,.i_rst_n                        (w_core_rst_n              )
            
,.iv_hcp_mid                     (wv_hcp_mid_hcp2tse     )
//,.i_local_cnt_rst                (w_local_cnt_rst_hcp2osm)      
//,.i_tsn_or_tte                   (w_tsn_or_tte_hcp2osm   )
,.i_sync_step_mode               (w_sync_step_mode_hcp2osm)
 
,.i_gmii_rxclk     (i_gmii_rxclk  )
,.i_gmii_rst_n     (wb_mac_rst_n[NUM_GMAC-1:0]  )    
,.iv_gmii_rxd      (iv_gmii_rxd   )
,.i_gmii_rx_dv     (i_gmii_rx_dv  )
,.i_gmii_rx_er     (i_gmii_rx_er  )
,.o_gmii_txclk     (o_gmii_txclk  )    
,.ov_gmii_txd      (ov_gmii_txd   )
,.o_gmii_tx_en     (o_gmii_tx_en  )
,.o_gmii_tx_er     (o_gmii_tx_er  )

,.o_osm_req_rx_pulse          (w_osm_req_rx_pulse_osm2hcp  )// hcp has no pulse
,.o_osm_resp_rx_pulse         (w_osm_resp_rx_pulse_osm2hcp )
,.o_osm_req_tx_pulse          (w_osm_req_tx_pulse_osm2hcp  )
,.o_osm_resp_tx_pulse         (w_osm_resp_tx_pulse_osm2hcp )

,.iv_local_counter				(wv_local_counter_hcp2tss)                               
 
,.i_data_wr_hcp                  (w_data_wr_hcp2tse)
,.iv_data_hcp                    (wv_data_hcp2tse  )  
,.ov_data_hcp                    (wv_data_tse2hcp  )  
,.o_data_wr_hcp                  (w_data_wr_tse2hcp)
 
,.iv_localclk                    (ov_localclk) 
,.i_cyclestart                   (o_cyclestart                         ) 
,.ov_schedule_period             (ov_schedule_period                   ) 
,.ov_tss_ver                     (wv_tse_ver_tse2hcp                    ) 
,.i_rc_rxenable                  (w_rc_rxenable_hcp2tss                 ) 
,.i_st_rxenable                  (w_st_rxenable_hcp2tss                 ) 
,.o_tsmp_lookup_table_key_wr     (w_tsmp_lookup_table_key_wr_tse2hcp    ) 
,.ov_tsmp_lookup_table_key       (wv_tsmp_lookup_table_key_tse2hcp      ) 
,.iv_tsmp_lookup_table_outport   (wv_tsmp_lookup_table_outport_hcp2tse  ) 
,.i_tsmp_lookup_table_outport_wr (w_tsmp_lookup_table_outport_wr_hcp2tse)   

,.iv_command                     (wv_command_hcp2hub      ) 
,.i_command_wr                   (w_command_wr_hcp2hub    ) 
,.ov_command_ack                 (wv_command_ack_hub2hcp  ) 
,.o_command_ack_wr               (w_command_ack_wr_hub2hcp) 

,.o_mirror_pkt_wr                ()  
,.ov_mirror_pkt                  ()  
,.o_PTO0                         (o_PTO0)
,.o_PTO1                         (o_PTO1)
,.o_PTO2                         (o_PTO2)
,.o_PTO3                         (o_PTO3)

);

endmodule            